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W972GG6JB
7.3
7.3.1
Command Function
Bank Activate Command
( CS ="L", RAS ="L", CAS ="H", WE ="H", BA0, BA1, BA2=Bank, A0 to A13 be row address)
The Bank Activate command must be applied before any Read or Write operation can be executed.
Immediately after the bank active command, the DDR2 SDRAM can accept a read or write command
on the following clock cycle. If a Read/Write command is issued to a bank that has not satisfied the
t RCDmin specification, then additive latency must be programmed into the device to delay when the
Read/Write command is internally issued to the device. The additive latency value must be chosen to
assure t RCDmin is satisfied. Additive latencies of 0, 1, 2, 3, 4, 5 and 6 are supported. Once a bank has
been activated it must be precharged before another Bank Activate command can be applied to the
same bank. The bank active and precharge times are defined as t RAS and t RP , respectively. The
minimum time interval between successive Bank Activate commands to the same bank is determined
by the RAS cycle time of the device (t RC ). The minimum time interval between Bank Activate
commands is t RRD .
In order to ensure that components with 8 internal memory banks do not exceed the instantaneous
current supplying capability, certain restrictions on operation of the 8 banks must be observed. There
are two rules. One for restricting the number of sequential ACT commands that can be issued and
another for allowing more time for RAS precharge for a Precharge All command. The rules are as
follows:
?
?
Sequential Bank Activation Restriction: No more than 4 banks may be activated in a rolling t FAW
window. Converting to clocks is done by dividing t FAW [nS] by t CK (avg)[ns], and rounding up to
next integer value. As an example of the rolling window, if RU{ (t FAW / t CK (avg) } is 10 clocks,
and an activate command is issued in clock N, no more than three further activate commands
may be issued at or between clock N+1 and N+9.
Precharge All Allowance: t RP for a Precharge All command is equal to tn RP + 1 x n CK , where
tn RP = RU{ t RP / t CK (avg) } and t RP is the value for a single bank precharge.
T0
T1
T2
T3
Tn
Tn+1
Tn+2
Tn+3
CLK
CLK
Internal RAS - RAS delay ( ≥ t RCD min)
Address
Bank A
Row Addr.
Bank A
Col. Addr.
Bank B
Row Addr.
Bank B
Col. Addr.
Bank A
Addr.
Bank B
Addr.
Bank A
Row Addr.
CAS - CAS delay time(t CCD )
t RCD = 1
Additive Latency delay(AL)
Read Begins
RAS - RAS delay time(≥ t RRD )
Command
Bank A
Activate
Bank A
Post CAS
Read
Bank B
Activate
Bank B
Post CAS
Read
Bank A
Precharge
Bank B
Precharge
Bank A
Activate
Bank Active ( ≥ t RAS )
Bank Precharge time ( ≥ t RP )
RAS Cycle time (≥ t RC )
Figure 12 – Bank activate command cycle: t RCD = 3, AL = 2, t RP = 3, t RRD = 2, t CCD = 2
Publication Release Date: Nov. 29, 2011
- 20 -
Revision A02
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